Sputtering deposition, such as Physical Vapor Deposition (PVD), is a process for depositing thin, highly uniform layers of a variety of materials onto many objects, for example depositing a metal layer over a substrate such as a wafer used in forming integrated circuits (ICs). In a direct current (DC) sputtering process, the material to be deposited (target) and the substrate to accept the deposited material (wafer) are placed in a special vacuum chamber. The vacuum chamber is evacuated and subsequently filled with an inert gas, such as argon, at low pressure.
The wafer is electrically connected to (or in the vicinity of) the anode of a high voltage power supply, the anode being generally at or near earth potential. The walls of the sputtering chamber are also placed at this potential. A target, typically formed of metal, is placed in the vacuum chamber and electrically connected to the cathode of the high voltage power supply. Alternately, the target is formed of an insulating material. An electric field is generated between the target (cathode) and an anode by the power supply. When a potential between the anode and cathode reaches 200-400 volts, a glow discharge is established in the inert gas in the superconducting region of the well known Paschen curve.
When a glow discharge operates in the superconducting region of the Paschen curve, valence electrons are torn from the gas and flow toward the anode (ground), while the resulting positively-charged ionized gas atoms (i.e., plasma) are accelerated across the potential of the electric field and impact the cathode (target) with sufficient energy to cause molecules of the target material to be physically separated from the target, or “sputtered.” The ejected atoms travel virtually unimpeded through the low pressure gas and plasma, some of which land on the substrate and form a coating of target material on the substrate. The result, under ideal conditions, is a uniform cloud of target molecules in the chamber, leaving a resultant deposition of uniform thickness on the chamber and its contents (e.g., the wafer). This coating is generally isotropic, conforming to the shape of the objects in the chamber. A natural consequence of this action is that the target material wears or becomes thinner as more material is sputtered.
The processing of integrated circuits is reliant on the uniformity of coating resulting from the glow discharge process. The vacuum chamber containing the discharge and target material is carefully designed to attempt to maintain a uniform electric field, and a glow discharge is, in principle, sustainable over a range of electric field strengths, again in accordance with the Paschen curve. However, uniformity of electric field cannot be maintained perfectly and the uniformity of the glow discharge and henceforth wear on the target is influenced by a number of factors, including thermal currents generated in the chamber and other mechanical anomalies, such as target misalignment. To compensate for these anomalies, commercial PVD sputtering machines often incorporate a mechanism to rotate a large magnet at constant speed above the target. This rotation serves to disturb the electromagnetic field in the chamber, focusing the region in which the plasma impinges upon the target on a smaller, moving area. Maintaining a constant power in the chamber while rotating the magnet at a constant rate improves the uniformity of wear of the target, increasing target life and generally maintaining a more uniform distribution of molecular target material in the chamber. As the magnet rotates above the target, local geometric, thermal and other variations cause the lumped electrical impedance of the chamber to change. With the power supply configured to deliver a constant power to the glow discharge, the relation between chamber voltage and current required to maintain constant power changes in accordance with the variation in impedance. If one monitors the chamber voltage and current, a clear periodic variation in the chamber voltage and current can be observed, with the period equal to that of the rotational period of the magnet.
Even with the rotating magnet mechanism in place to attempt to stabilize the glow discharge, certain conditions can result in a local concentration of the electric field causing the glow discharge to pass from the superconducting region of the Paschen curve into the arcing region. Arcing during PVD results in an unintended low impedance path from the anode to the target through electrons or ions in the plasma, the unintended path generally including ground, with the arcing being caused by factors such as contamination (i.e., inclusions) of the target material, inclusions within the structure (e.g., surface) of the target, improper target alignment (e.g., misalignment of cathode and anode), vacuum leaks, and/or contamination from other sources such as vacuum grease. Target contaminants include SiO2 or Al2O3.
Arcing during PVD is one cause of yield-reducing defects in forming integrated circuits on semiconductor wafers. While normal metal deposition is typically less than 1 micron thick, arcing causes a locally thicker deposition of metal on the wafer. When an arc occurs, the energy of the electromagnetic field of the chamber is focused on a smaller region of the target than intended (e.g., the neighborhood of the target defect), which can dislodge a solid piece of the target. The dislodged solid piece of target material may be large relative to the thickness of the uniform coating expected on the wafer, and if a large piece falls upon the wafer, it may cause a defect in the integrated circuit being formed at that location. Subsequent photolithography processing etches away various areas of the deposited metal layer, leaving metal conductor paths according to desired circuit patterns. Because arcing results in a localized defect (area) having a greater thickness than the surrounding metal, the defect area may not be thoroughly etched in the subsequent processing, resulting in an unintended circuit path (i.e., short) on the chip. A semiconductor chip has multiple metal layers separated by insulator layers, each of the metal levels formed by depositing, patterning and etching a metal layer as described above. A local defect in one layer can also distort an overlying pattern imaged onto the wafer in a subsequent photolithography step, and thus result in a defect in an overlying layer.
Manufacturing a wafer of modern integrated circuits can involve well over a thousand individual processing steps, the value of the wafer and consequently each individual integrated circuit die increasing with each processing step. Arcing in a PVD sputtering apparatus used to process wafers into integrated circuits can render portions of the wafer useless for its intended purpose, thereby increasing manufacturing costs. Using target materials free of arc-causing inclusions is one way of minimizing integrated circuit fabrication defects; however, target material may become contaminated during its manufacture or thereafter. Discovering target contamination prior to sputtering operations so as to prevent arcing defects is costly, both in terms of time and expense. Not discovering arcing defects in a timely manner is similarly costly in terms of random yield loss, for example by the manufacturer operating a deposition chamber until the target inclusion causing the arcing is sputtered through. Furthermore, when a solid piece of the target is dislodged during an arc, the surface of the target may be further damaged and the potential for future arcing in that neighborhood increases.
Absent real-time arc detection, corrective action is dependent upon the availability of parametric data. It is costly to measure the number of defective layers caused by arcing, for example via electrical tests designed to reveal shorts or by scanning the surface of wafers with a laser after metal deposition. These tests take time to run, during which production is delayed, or undetected yield loss occurs for an extended time. Since a defect such as a short at any level can impact integrated circuit functionality, it is desirable to avoid damage resulting from arcing during sputtering deposition.
Accordingly, real-time arc detection permits faster identification of sources of yield loss, and detection of incipient faults within the processing tool or target itself, both resulting in more efficient integrated circuit fabrication applications.
As discussed above, arcs can throw solid material into the chamber, and it can be assumed that any such piece of solid material landing on a wafer of integrated circuits has a high probability of damaging at least one integrated circuit. One statistic indicative of the potential damage to a wafer of integrated circuits is therefore the number of arcs that occur during a process step. It is also reasonable to assume that the expected damage caused by an individual arc to an integrated circuit wafer is a monotonically increasing function of the energy delivered to the arc, since a violent arc is likely to spread more solid material over a wider area than a relatively “mild” arc. A system that can estimate both the number of arcs occurring during a PVD sputtering process step as well as the severity of the arcs in real time is therefore a valuable tool in estimating the potential damage caused in a particular PVD sputtering step.
It is well known that when an arc occurs in a glow discharge process, the magnitude of the lumped impedance of the chamber decreases rapidly. When this occurs, the presence of series inductance in the driving point impedance of the power delivery system, comprising power supply and interconnection means, causes a rapid drop in the magnitude of observed voltage between the anode and cathode of the chamber. Observing the chamber voltage and comparing it against a fixed threshold is a common means of detecting the presence of an arc and one can readily accomplish this by attaching a common oscilloscope to the cathode, with the ground of the oscilloscope probe attached to the chamber. Having an estimate of the average chamber processing voltage, which one can obtain visually by observing the voltage using a free running oscilloscope, one can set the trigger point of the oscilloscope at a voltage greater than the expected voltage (the voltages observed in such a manner are negative with respect to the oscilloscope reference). When the oscilloscope triggers, the resulting voltage waveform due to the arc can be observed and one can also simultaneously observe the current by means of an appropriate current probe. Systems have been developed that emulate this method of detecting arcs and which count the number of occurrences so obtained over the course of a processing step. A known shortcoming of this approach is that the fixed trigger level must be set conservatively, as the chamber voltage varies periodically with magnet rotation as discussed above, as well as varying over the course of a PVD processing step due to thermal and other considerations. As such, such a system may miss arcs of small magnitude, which nonetheless cause damage. A system that can more closely follow the actual, instantaneous expected chamber voltage would permit these arcs to be detected more readily, providing a more accurate estimate of damage.
In the PVD process used to produce integrated circuits, arcing conditions lasting less than 1 microsecond are commonly observed. These short duration arcs are commonly called microarcs. Electronically controlled analog or switching power supplies cannot react to this rapid change in chamber impedance during a microarc. As a natural consequence of the series inductance, the power supply delivers a near constant current to the chamber during a microarc. Assuming that during an arcing condition, all energy delivered by the power supply is focused on the arc, the energy delivered to an individual arc can be estimated by the integral of the product of the power supply voltage times the (assumed constant) current over the interval of the arc. Again, digital oscilloscopes exist that permit the capture of both the chamber voltage and current waveforms during an arcing condition. Computer software, such as Tektronix “Wavestar” software, exists that can permit a digitally stored waveform to be uploaded to a computer, where the captured voltage and current waveforms can be subsequently multiplied point by point to compute instantaneous power and that power waveform integrated over the duration of the arc to determine the overall energy delivered by an arc.
While useful for gaining an understanding of the arcing phenomenon in PVD applications, this method of computing arcs and arc energy using an oscilloscope and a post processing computer is of little value in production applications. Even modern handheld oscilloscopes are relatively bulky instruments, and real estate in an integrated circuit clean room is extremely valuable. A stand alone post processing computer also takes up valuable floor space and would likely need to be located outside the clean room and connected to the oscilloscope by a network, adding latency in the transfer of data between the oscilloscope and computer. Furthermore, there is no means to tell a-priori the duration of an individual arc, or the frequency at which they might occur, leaving the problem of exactly how to set the controls of the oscilloscope. Oscilloscopes also have limited waveform storage capability, and therefore prone to losing information at the times in which it is needed most, when there is much arcing activity during a process. A system so configured would render real time control and decision making impractical.
Various aspects of the present invention address the above-mentioned deficiencies and also provide for arc detection methods and arrangements that are useful for other applications as well.
In addition to the problems discussed, when counting arcs only as voltage threshold violations, some information may be lost or obscured if the power supply responds to the arcs by reducing delivered power. The result of reducing power is a dip in both the voltage and the current.
While determining the severity of cathode-anode or target arcing in a physical vapor deposition chamber is a major concern, the occurrence of non-cathode arcs (NCAs) in the chamber is also problematic. When NCAs occur, arc energy monitored with respect to cathode arcing typically remains zero. It is believed that such NCAs result from charging of an electrically isolated chamber component, namely the deposition ring or the cover ring, and the sudden dissipation of the charge to the wafer or a chamber component in close proximity to the wafer. This presents a problem of how to indicate the occurrence of, or the potential of the occurrence of such NCAs.
The present invention is provided to solve the problems discussed above and other problems, and to provide advantages and aspects not provided by prior systems of this type. A full discussion of the features and advantages of the present invention is deferred to the following detailed description, which proceeds with reference to the accompanying drawings.